SerDes in FPGA: Importance to Overall FPGA Performance and Functionality

Key Takeaways

●     Learn about SerDes functionality.

●     Gain a greater understanding of how SerDes works in FPGAs.

●     Learn how FPGAs enhanced by SerDes increase performance and functionality.

Electronic circuit board with SerDes-enhanced FPGAs.

Whether you are converting a website visitor into a revenue-generating customer or converting a fraction into a decimal to solve a mathematics problem, the ability to convert accurately is essential.

In the field of electronics and high-speed communications, the ability to convert serial data into parallel data is critical to overall functionality. In the case of high-speed interfaces, there is a device specifically designed for such tasks, and it is called a Serializer Deserializer (SerDes). So what functionality can SerDes in FPGAs offer? Let’s dive in. 

What Is a SerDes?

A SerDes is an integrated circuit or device used in high-speed communications that converts between serial data and parallel interfaces, in either direction. There are a variety of applications and technologies that use a SerDes for the principal purpose of providing data transmission over a differential or single line by minimizing the number of input/output pins and connections.

In terms of functionality, a SerDes chip enables transmission between two points that use parallel data over serial streams, thus mitigating the number of data paths required for the data transfer. This reduces the amount of needed connecting pins which keeps the wires and connectors small and thin. Furthermore, the transmitter side handles the conversion of parallel data to serial data, whereas the receiver side performs the opposite function.

In summary, a SerDes chip converts parallel data into serial data so that it can travel over media that does not ordinarily support parallel data. A SerDes can be helpful in circumstances where there is a need to preserve bandwidth.

What Are FPGAs?

A field-programmable gate array (FPGA) is a chip that can be programmed and reprogrammed to perform numerous functions at any point in time.

Furthermore, thousands of units called logic blocks comprise a single chip, and these blocks link via programmable interconnects. The FPGA’s circuit is made by connecting several configurable blocks, and it has a rigid internal structure. An FPGA is essentially a programmable version of an ASIC.

Overall, the FPGA affords general functionality that allows programming to your specifications. However, like most things in life, there are side effects to the FPGA’s versatility. In this case, this versatility comes at the cost of increased price, increased internal delay, and limited analog functionality.

Applications of FPGAs

The following are some of the applications for FPGAs within the area of electronics:

• Video surveillance

• SPLDs

• Motor controls

• Device controllers

• Communication filtering and encoding

• Emulation of entire large hardware systems (interconnected FPGAs)

• Computers

SerDes in FPGA

With FPGAs, both the transmission and receiving of data utilizes a SerDes. The merging of FPGAs and high-speed SerDes technologies introduced the field of electronics to SerDes-enhanced FPGAs. Their emergence provides a cost-effective substitute to ASICs in applications that require a multi-Gigabit data link--for example, across a PCB (cable or backplane).

This particular class of programmable devices is increasingly promoting design changes due to the increase in cost-effective and low-powered devices. Overall, FPGAs continue to advance from their origins as a collection of gates and routing to what we see now--managing tasks from AI to communications.

FPGAs, like graphics processing units, are experiencing significant changes from their initial inception, which utilized a more focused view of the solution space. Like the majority of electronic devices, FPGAs began as single chips. Although there is an increase in their size in terms of transistors, their architectural base is evolving as well.

How SerDes Works in FPGAs?

In terms of wired communications, there are two types; parallel and serial. When we refer to parallel, we are referring to PCI and LPT, etc., whereas when we refer to serial communications, we are referencing USB, HDMI, or Lightning cables.

Characteristically, parallel communication utilizes more pins, less power, limited speed, low bandwidth, and, overall, is less complicated. In contrast, serial communication uses fewer pins, is faster, has higher bandwidth, uses more power, is more complex, and is poised for the future as well as the present.

As you can imagine, parallel vs. series communications are ideal for different types of applications, and both have their advantages/disadvantages. When utilizing parallel to transmit more data, you have two general options: Option one is to use additional paths, and option two is to increase your clock speed. In summary, there are three primary issues with attempting to increase the data you are transmitting when utilizing parallel.

Communication Methods Continued

One of these primary issues is clock skew. Clock skew is the occurrence in digital circuit systems (synchronous) in which the same sourced clock signal arrives at different times to different components. The discrepancy between the readings of any two clocks is called their skew. As the clock speed increases, the issues with skew are more apparent and problematic.

Another issue that requires special attention when increasing transmission data amounts is wire length. Two factors warrant attention: firstly, wire length is critical, and the rule of thumb is one-foot propagation in 1ns (1Ghz = 1ns period). Secondly, for this reason, the physics of the length is vital because if two lines are not exact, it will cause data to arrive at different times. This causes a loss of transmission functionality (unrecoverable data).

To afford more significant amounts of data transmissions without incurring clock skew, we use serial transmission methods. Serial communications utilize a clock embedded in the data, which means that the transmitter encodes the clock and data together. The receiver extracts the clock and data separately. As I am sure you are aware, we utilize the clock to sample the data.

Serial Transmission in FPGAs

When using serial transmissions, there are three areas of focus:

• Clock encoding scheme

• Channel optimization

• Output and input stages of the FPGA

Clock Encoding Scheme

The function of the clock encoding scheme is to guarantee data transitions; for example, long data of all 0s needs transition (i.e., it needs an encoding scheme). Encoding scheme examples include:

• Manchester

• HDLC (High-Level Data Link Control)

• 8B/10B (currently the most popular)

We will discuss 8B/10B in more detail since it is the most popular. As its name implies, 8B/10B takes 8-bit data and converts it into 10-bit data. Although this is a 25% hit on your available bandwidth, it is a worthy trade-off. The trade-off here is, it will guarantee DC (direct current) balance of your line (running disparity). Another aspect of this trade-off is it ensures transitions for CDR (clock data recovery) on your receiver.

The 8B/10B encoding scheme is not only the most popular but is also very common. We can find it in use with DVI, Display ports, Ethernet, Firewire, HDMI, PCIe, SATA, and USB.

Channel Optimization

Channel optimization refers to the cable interface itself. In terms of data transmissions, there are two types:

• Single-sided

• Differential

All high-speed data is differential and requires one extra pin, but the trade-off is worth it. The compromise here affords increased speed and longer cable runs. Also, there are factors to consider when addressing channel optimization. They include:

• Cable construction quality

• The resistance, capacitance, and inductance of the copper wire within the cable

We measure channel quality by utilizing an ISI (intersymbol interference) diagram, which we also call the eye chart.

FPGA Output Input Stage Optimization

The FPGA consists of output and input stages that are critical to overall functionality. These stages are responsible for both the pre-emphasis and post-emphasis. The pre-emphasis is a brief over-driving of the line (LVDS 0.35V) of a video or audio signal before transmission. This results in quicker transitions and improves performance.

Note: LVDS is Low-voltage differential signaling.

Serial Communication and FPGAs

FPGAs are ideal for serial communications because they are fast and have SerDes blocks built-in. The importance of SerDes to FPGA functionality is vital. FPGAs with built-in SerDes blocks make them ideal for radar systems in military applications, networking, high-speed Tx and Rx, and surveillance.

The use of built-in SerDes in FPGA provides increased performance, functionality and offers a broader array of applications than an FPGA is ideally suited for. Lastly, SerDes in FPGA also minimizes the number of input/output pins and connections, while providing data transmission over a differential or single lines.

SerDes-enhanced FPGAs are used in many applications.

Successfully implementing components like SerDes-enhanced FPGAs into your electronic designs requires using the right set of PCB layout, design, and analysis software. Allegro PCB Designer, and Cadence's full suite of design tools, can help you create designs from verified component models and analyze all aspects of functionality. You will also have access to a set of tools for MCAD design and preparing for manufacturing. Having the right software at your disposal ensures that you can create high-quality designs and get them right the first time. 

If you're looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.