Interconnect Design in Low Power VLSI

March 4, 2021

Cadence PCB Solutions

Key Takeaways

The goal in low power VLSI design is to combine circuit blocks into an integrated circuit while keeping power consumption and delay times low.
Interconnects should be designed with optimized power flow to ensure signals transition through an integrated circuit.
Although there are many solutions to keeping power low, interconnects need to be designed to balance power draw, propagation delay, and SNR.

Interconnects should be designed to support low power signals in these CMOS ICs.

VLSI is the standard process for aggregating CMOS transistor blocks into a large integrated circuit, but CMOS interconnects are not always power efficient. Interconnects include much more than just the physical transmission line laid out across a semiconductor die, and all sources of power generation and dissipation must be considered to design power-efficient systems. Interconnect design in low power VLSI aims to reduce power consumption while maintaining signal integrity as signals are transferred around the system.

Why Worry About Power in VLSI?

As part of scaling transistor architecture and passive components in ICs, power dissipation becomes an important design constraint and requires optimization throughout interconnects. One goal of interconnect design in low power VLSI is to reduce power consumption where possible, particularly in high-speed digital circuit blocks. There are several reasons power consumption becomes a major design constraint in VLSI:

Transistor count: As devices scale, the number of transistors increases, so the power consumption per transistor needs to go down. In particular, for CMOS devices, the power consumed by a CMOS inverter during switching needs to be minimized.
Signal swing: During switching, the signal swing between states will draw large power as transient currents. This is one reason signal levels drop as transistor scaling continues.
Faster clocks: More frequent switching dissipates more power before heat can be dissipated into packaging, leading to high die temperatures and device failure.
System power: More devices are being run on batteries rather than wall power, so total power consumption needs to be minimized to extend device lifetimes. Complex PLDs and processors are major drivers of power consumption in mobile devices and embedded systems.
Noise immunity: Power consumption needs to be kept low, but bringing power too low brings digital signal levels to the point where SNR values are getting closer to 1.
IR drop on interconnects: All metal interconnects in an IC have some DC resistance that will dissipate power carried by a propagating signal. As devices scale, smaller interconnects are preferred, but these will dissipate more power.

Many of these points relate specifically to interconnect design in low power VLSI, while others relate to the interactions between a given IC and the larger system. Some simple design choices can help keep power consumption and losses low on interconnects while maintaining signal integrity, and simulations can aid design verification before prototyping and testing.

How to Reduce Power Consumption in VLSI Interconnects

Power consumption in VLSI design and layout must be focused on four areas: circuit-level, system-level, architecture-level, and network-level. Circuit-level and architecture-level design choices can happen on the semiconductor die and provide two standard ways to reduce power consumption.

Architecture-Level Design Techniques

The system architecture and routing topology are two broad areas where power consumption can be reduced. Circuits in each region of an interconnect (driver, receiver, buffers, and repeaters) can be simplified to reduce total power draw, either by redesigning logic or consolidating circuit blocks.

Modifying the bus topology is another area in a VLSI layout where the architecture can be optimized to have low power. In particular, bus splitting is one method for reducing the capacitive load on an interconnect. Switching to a mesh network-based bus topology is another method for reducing interconnect power consumption in a layout.

Bus interconnect design in low power VLSI

This VLSI layout uses a linear bus topology, but an alternative like point-to-point or mesh topology might provide lower power consumption.

Circuit-Level Design Techniques

VLSI interconnects already use repeaters and buffers to decrease propagation delay, but switching in digital signals is still power inefficient. To reduce power consumption during transient signal swings, the supply voltage can be reduced somewhat to reduce power draw. Wire capacitance can also be reduced by using wider wires (which also decreases IR drop), which will further decrease the switching time once the supply and signal levels are lowered.

Power Optimization for Interconnect Design in Low Power VLSI

Once simulation results have been produced with a circuit simulator, low power VLSI interconnects need to be optimized to run at low voltage and current levels without signal degradation. The best circuit design tools can help with optimization by running parameter sweeps for different, real, or phenomenological circuit elements in an interconnect. By iterating through candidate parameter values in an interconnect design, the power consumption can be minimized while balancing other design goals like signal integrity.

Parameter sweeps are useful for running the following calculations in quick succession and deriving design results:

Electrical characteristics	Type of simulation
Interconnect transfer functions	Identify poles and zeros in the transfer function, and simulate the impulse response in interconnect sections to ensure signals are not distorted.
Transmission line impedance	Check that impedance is matched to the load impedance at the receiver end of the interconnect.
DC resistance and power loss	Use the DC resistance and your interconnect current to calculate power loss (IR drop) and ensure the receiver sees sufficient signal level to prevent bit errors.
Transient analysis	Use this to examine signal swings and calculate average power consumption
Noise analysis	Use noise analysis to determine an appropriate limit for SNR to ensure signals can be resolved above the system’s noise floor.
Other tasks like temperature and yield analysis	Check that the optimized power is stable throughout the system’s intended operating temperature.

Running parameter sweeps in these analyses also allows power consumption to be determined, and other design metrics can be examined to ensure correct system operation. The best circuit design and simulation software will help automate these analyses with a SPICE-based simulation engine.

When you need to perform interconnect design in low power VLSI, use the front-end design software from Cadence to start creating your circuit schematics and access simulation tools. The PSpice Simulator application includes an array of integrated circuit simulation features that are ideal for advanced electronics. You’ll have a complete set of tools to create and simulate your circuits and you’ll also be able to perform parameter sweeps needed to minimize power consumption in your VLSI designs.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.