How a Power Supply’s VRM Control Loop Works

Unless you want your switching regulator or VRM output to drift during operation, your circuitry will include a control loop that compensates for changes in the output voltage and/or current. PMICs can have a complex control loop that is accessed via a feedback pin on the chip package. This feedback pin essentially takes a measurement of the output voltage and attempts to compensate for fluctuations in the output power.

Not all feedback loops are created equal. Depending on what you connect to that feedback loop, such as filtering circuits or even ferrites, the feedback loop in your system may not function as expected. In addition, depending on the frequency range you work in, feedback loops can respond unexpectedly, such as responding slowly or responding by entering a sustained oscillation. So before you muck around with filtering on a feedback loop, make sure you select a power regulator that will function correctly with your particular circuits.

Power Supply Control Loop Topology

The control loop in a power supply accepts feedback from the output voltage and compares this with a reference voltage. Through this comparison, the power supply can adjust its output based on fluctuations in the output voltage. Essentially, the power supply control loop is an amplifier-based circuit.

If you look at a datasheet for a VRM, the control loop can be a bit complex. The driving circuitry for switching can also be rather complex and is typically a black box in the component’s block diagram. For example, take a look at the block diagram below for part number 1 2 3 4.

Front-end interface for this power supply control loop is outlined in the red box. Source: LMZ35003 datasheet.

The amplifier portion of the control loop as well as the control circuitry will determine how fast the power supply can respond to fluctuations in the output voltage. This is a main factor that determines whether a power supply’s control loop can support certain types of components. There are three typical operating regimes:

• DC voltage - The VRM or switching regulator only needs to supply DC power and output voltage fluctuations are slow

• Mid-range frequencies - This is the most common operating area as it corresponds to power demands in most digital ASICs

• High frequencies - This range corresponds to large processors with many fast digital interfaces, which may run at lower core voltages

Remember that in all of these frequency ranges, the regulator is reading the output voltage and feeding that back into the regulator. Depending on what is placed at the regulator output, this could affect the feedback loop operation in the same way as we typically see in amplifier circuits. Here are the three operating regimes explained in detail.

DC Operation

If the power regulator only needs to supply stable power at DC and address noise at very low frequencies, the control loop does not need to respond very fast. Inductive and reactive components can both be used to filter noise and stabilize the power output to the DC load. This could allow the use of a ferrite in order to block high frequency noise from reaching a DC load.

In these power situations, output capacitance is usually sufficient to stabilize the power output. If there is a disturbance at the load and or some other kind of power fluctuation, the output capacitance could discharge and this would stabilize the output power. In these instances, the control loop just responds to this discharge rather than attempting to track changes in the output power.

Mid-Range Power (up to 100 MHz)

Most digital ASICs will require power up to the 100 MHz range, and the control loop can attempt to stabilize power to these devices. When constructing the PDN to support stable power to these ASICs, the power is stabilized by ensuring there is enough capacitance and low impedance up to very high frequencies. Ideally, a PDN impedance curve will be below some target impedance up to very high frequencies, as shown in the graph below.

High PDN impedance above about 100 MHz creates transients that can be difficult for a VRM’s control loop to regulate.

The reason we need this low impedance is that the capacitance in the PDN needs to respond to power demands from digital ICs. The control loop’s job is to have a sufficiently fast response to replenish energy to the capacitance in a short enough time to prevent power droop and noise. When a transient response occurs on the power bus, the control loop can attempt to compensate for it by adjusting the output page while also supplying charge to capacitors. Large switching regulators operating at high kHz to MHz switching frequencies can typically respond within the required time frame to help stabilize the power on the PDN.

GHz Frequencies

Once you get to the GHz range, it can be difficult to find power regulators that can respond to fluctuations fast enough to maintain stable power. The control loop in this frequency range becomes sensitive to any additional inductance in the feedback line. As a result, it can be difficult to respond to extremely fast power draw or or large current draws with slower edge rate.

This is the domain of large processors with very high I/O counts, such as FPGAs. This is also the domain of specialized components that include extremely fast interfaces, such as processors for high-speed networking architecture. From the above PDN curve, we can see the range where the on-PCB (off-chip) PDN starts to become inductive. This is shown in the graph below.

Up to 1 GHz frequencies, the on-chip portion of the PDN normally addresses the inductive vertical slope in the off-chip portion and attempts to keep the PDN impedance low in this range. This would be done in three possible ways:

• Using on-chip capacitance, substrate capacitance, and die capacitance to stabilize power

• Using on-chip active power regulation in the semiconductor die or in an active interposer

• Via compensation from the VRMs control loop

The last point is where the control loop comes in. These chips can excite a transient with a power spectrum in the 100 MHz to 1 GHz range, and these transients can have relatively high amplitude due to the inductive slope on the PCB portion of the PDN impedance curve. The VRM control loop could attempt to compensate for this fluctuation in power if it is fast enough.

There are two points that determine whether the PDN can respond fast enough to these fluctuations: fast edge rate at low current, or slow edge rate at high current. Obviously, this creates a challenge in selecting a switching regulator that can support these very high frequencies, because not all switching regulators are created equal.

How to Learn About Your Control Loop

When trying to select a VRM that can assist power stabilization in your PCB, it can be difficult to find components if you don't know which specifications to look for. If you start looking at graphs in the datasheet, you'll find that there is no “transient response” type of graph as a function of frequency. Components with feedback and control loops generally do not specify their performance in this way. Instead, the performance of the control loop is specified using a gain-phase plot. A datasheet graph for the Texas Instruments LMZ35003 voltage regulator shown above is found below.

Front-end interface for this power supply control loop is outlined in the red box. Source: LMZ35003 datasheet.

This graph shows the gain and phase of the control loop transfer function; you may have seen similar graphs in amplifier datasheets, particularly for op-amps. As we get to higher frequencies, we see that there is a phase shift that becomes more negative. Eventually, the phase margin is such that the control loop actually reinforces noise via the act of attempting to compensate for it. This could lead to oscillations during the transient event rather than a suppressed transient.

The Ideal VRM Response

To select a VRM for high-speed digital systems, you should look at these curves to determine whether the VRM can compensate for your expected output voltage fluctuations. One thing you should note is that the control loop response is a function of the output voltage, output currents, and the amount of capacitance seen at the output pin. We can see this from the graph above. Moderate changes in the amount of total output capacitance will change this gain phase curve. Inductance in the feedback loop will also change the shape of the curve.

In summary, select a VRM that provides sufficient phase margin up to the frequency levels you need to address in your design. This could mean reaching well into the MHz range in order to provide stable power to your processor and other components. If you have a SPICE model for your VRM component, it is possible to simulate the VRM response in the time domain for various loads being drawn from the PDN.

Advanced digital systems require comprehensive analysis in terms of signal integrity and power integrity, and both dimensions of system performance relate to the VRM response in your system. Multi-disciplined design teams rely on the best set of PCB design features in Allegro PCB Designer from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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