What's Needed to Get to kA Currents on a PCB

Power demands for digital systems, especially large digital processors with fast I/Os, have been well detailed by many leading engineers in the industry. Getting to very high currents demands efficient power regulation and delivery of that power with minimal loss. When digital systems scale up to hundreds or thousands of Amps of current, the challenges of noise and heat become extreme, with both being related to PDN impedance.

Digital systems running with very high currents demand low PDN impedance, a characteristic which is standard for any digital system. The other factor to consider is keeping fluctuations in the output voltage from a power system to be highly stable. This is not the type of thing you can just plug into a PCB from an external power unit, keeping noise low and voltage stable demands placing the power stage directly on the same PCB as the processor.

When we look at leading edge companies who are implementing solutions in this area, we see some common threads and approaches:

• Highly parallelized VRM architecture
• Extremely low PDN impedance
• Packaging that aids high current delivery

Keep reading to see how high compute infrastructure designs can reach kA levels.

kA Current Starts With Boards and Circuits

Getting to power efficient kA current levels for digital systems requires major successes in two areas: the PCB and VRM circuit design. We often assume that circuits will operate in perfect accordance with schematics and, as a PCB designer, your only responsibility is to build the best board. In reality, they have to work together, especially between the layout circuits and overall construction of the board.

First, let's look at the circuit aspect, and particularly the voltage regulator selection aspect.

VRMs Supporting kA Currents

There is no single regulator chip that supports extremely high current. Power regular modules are DC/DC converter modules that can handle a lot of power, but very few can operate at the level of hundreds of amps of current. Furthermore, VRMs have to operate at very low logic levels, which creates a challenge from the perspective of noise injection into the output from a regulator module. Low logic level means lower noise margin in logic circuits, and so the PDN impedance connecting VRMs needs to be minimized.

The typical VRM architecture for large digital components uses a parallel group of VRMs to provide high stability regulation over a common PDN in the PCB. The PDN then connects to the processor’s BGA package through a large group of power and ground vias.

The PDN architecture shown above uses a parallel group of VRMs such that the total current supplied by the modules reaches the level required on the core logic rail. VRMs supply the same rail to share their current across a large copper region, which then reaches the microprocessor.

These VRMs broadly have 5 important characteristics:

• Multiphase topology
• Non-isolated buck topology
• Low duty cycle (large step-down)
• Fast control loop
• Current-mode control

Typical VRMs used for large processors are multiphase converters that use 3 or 4 switching phases. Since high compute architecture comes into a device at high voltage, it will be stepped down in a non-isolated buck topology, which demands very low duty cycle (about 10%) and thus high inductance to ensure operation in continuous mode (CCM). Each phase in an individual VRM supplies a fraction of that VRM’s total current output, and this is scaled in parallel to supply all the current required by the processor.

With these VRMs running at low duty cycle per phase, high frequency per phase (MHz values), and with 3 or 4 phases per VRM, a single VRM is able to equivalently operate as a very high frequency DC/DC converter module. This reduces the noise and the size of the required power supply components, namely the output inductors needed for noise reduction. Further filtering on the output is applied with additional bulk capacitance as needed. The remaining capacitance is placed close to the power pins on the processor (more on this below).

PCB Layout Aids Fast VRM Noise Response

The above description addresses specifically the noise associated with regulation to a DC current. However, it is known that a digital processor creates AC noise on its own power rail. Some of this is addressed at the circuit level with component selection, but there is an important specification that is required to ensure AC disturbances on a DC rail can be compensated: the VRM feedback loop’s frequency response.

This is where the PCB layout first starts to affect the voltage control capability of the VRM. A multiphase synchronous buck converter VRM has a complex feedback sensing and PWM control circuit internal to the component. This component requires a set of feedback resistors that provide a measure of the output voltage into an error amplifier, as shown below.

IMAGE: VRM Circuit with feedback amp

The PCB layout starts to matter here due to the placement of the feedback resistors. How do we ensure the control loop can respond sufficiently fast to voltage disturbances on the output rail? We have to appropriately place the feedback resistors, inductor, and other parts in a tight loop as would be typical for any switching regulator circuit.

An example of placement in these power circuits is shown below. These circuits have been mostly replicated to illustrate how the circuits can be effectively paralleled to provide high current. The example below shows only three regulators; when kA currents are required in the most advanced processors, don’t be surprised to see dozens of these replicated circuits spanning the perimeter of a water-cooled processor.

Example layouts of VRM circuits in parallel.

What isn’t visible in the above circuit is the internal control circuitry of the VRM components. These components use an error amplifier and comparator circuit to adjust the PWM duty cycle and regulator the target voltage output. When AC fluctuations occur, those can be measured by the VRM’s feedback circuitry and the VRM can attempt to respond by adjusting the duty cycle. Faster loop response equates to better regulation against AC fluctuations, and a faster loop response requires reducing inductance in the feedback loop.

This is why, in the below image of a motherboard, the VRMs are placed around the exterior of the processor, and not placed near the typical corner of the board where the main system power comes in. By placing these VRMs around the perimeter of the processor, the placement ensures there is minimal inductance on the output rail and that the feedback resistor network is close to the power pins. It helps to minimize parasitic inductance back to the feedback pin on the VRM component which helps to reduce high frequency attenuation in the control loop response.

VRM circuits on this motherboard are placed around the central processor socket.

PDN Impedance and kA Currents

What is discussed above gives a good overview of feedback loop response and the functions of VRM circuits, but how does this scale up to kA current levels easily? This involves scaling up the number of VRMs in parallel, as mentioned above. This already requires a level of synchronization across VRMs that ensure on-time power delivery by each circuit in the array, but it does not address other important points in the layout. The next big challenge on the PCB is the impedance of the PDN.

PDN impedance is responsible for transforming highly irregular high current spikes drawn into a large processor into voltage noise seen on the voltage rail. These voltage fluctuations would be measured at the I/O supply pins and thus could appear as noise on the I/O output voltage level. At a given current level, the expected voltage fluctuation due to a current disturbance is described simply by Ohm’s law:

V = IZ(pdn)

In reality, it is more mathematically complex and involves some Fourier transforms, but this gives an estimate of the target PDN impedance at a specific voltage and current.

To reach kA currents within approximately 1% of a low core voltage level (such as 1.0 V), the PDN impedance target would need to be:

0.01 V/1 kA = 10 micro-Ohms, flat up to 100 MHz to 1 GHz

This is an extremely low value for PDN impedance that demands multiple approaches to the target value can be reached. Furthermore, getting to such a low impedance comes with the additional requirement that the low impedance curve span up to approximately 100 MHz to 1 GHz bandwidths, depending on the processor being powered.

Bypass capacitors in small case sizes can only do so much for providing low PDN impedance, and eventually you will reach the PDN impedance target and start seeing inductive behavior above a few dozen GHz. Getting flat PDN impedance above 100 MHz requires:

• High die capacitance
• Chip capacitance in-package
• High plane capacitance

So far, signal integrity and power integrity domains remain separated in many ways due to the lack of power-aware signal integrity modeling methodologies. Complete modeling of the power supply circuits, PCB layout, and response on the chip is still very involved and requires a linear network approach to evaluate VRM-PCB-processor behavior. EDA vendors are working towards complete approaches to power-aware signal integrity simulation that can address all of these aspects in a single analysis workflow.

Design teams building the most advanced digital hardware rely on the comprehensive set of PCB design features in Allegro PCB Designer from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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