Cadence Live 2022 - A Chance to Network and Learn How Others Have Succeeded

The sprawling Santa Clara Convention Center was decorated with signage that made this tech fair seem almost intimate. Sign-in was easy as long as you can find that picture of your shot record. Health and safety precautions are here to stay, it seems. Then, there’s the continental breakfast and the mask has to come off. That’s our world in a microcosm.

Cadence Live is a world tour with guest speakers from companies that run the various tools including OrCAD and Allegro. The thing is that there are other tools that can be used to solve very specific problems such as optimizing low-power systems. Maybe I can’t justify owning that piece of the puzzle but could benefit by meeting an expert who runs the simulations as a service. In any case, it’s good to know what is out there, especially if you’re producing leading edge products.

As you’d expect, there is always a focus on chip design and verification. The PCB layout is an extension of that central effort with the substrate and/or module as a go-between. Each of these tiers, chip, substrate and PCB is an ecosystem of its own.

Figure 1. Image Credit: Author - Sweeping through the displays ahead of the first breakout sessions.

You might even see enough interesting stuff to make you want to get into chip layout or in the gap between bare dice and printed circuit boards. Additive processes similar to those used on substrates are making their way into the printed circuit boards under the banner of MSAP (modified semi-additive process). This is a different process where only certain layers on the PC board are candidates for the ultra-thin traces.

That said, you might be surprised at how much overlap exists between substrate design and PCB design as far as the tools are concerned. For instance, if we use chip-on-board (COB) technology, that is akin to making the PCB a substrate. The substrate tools are a superset of Allegro. It’s pretty nice to enter a few parameters and automatically generate a wirebond cage. If you’re doing enough of that kind of work, it could be worthwhile to consider using a tool that is specialized to your flow.

Figure 2. Image Credit: Author - No line for the continental breakfast.

The best education is learning the stuff that you’re going to actually use so the PCB track is the main course for us. Further topical divisions for photonics or automotive and other subdivisions fleshed out a number of industry-specific tracks. Meanwhile, the room could easily have held double the number of people who showed up. It was a relief that we weren’t packed in.

Migrating a Diverse Group of Corporate Divisions to a Centralized PCB Library

One talk on the PCB track that I was looking forward to was on the centralization of the PCB footprint library at Microsoft. This is a company that has a reputation for not working together and being siloed off with little to no overlap. I was there when this idea was initially floated around. We had people who were rather entrenched in their process and weren’t likely to evolve at this point in their career. In some circles, these folks are referred to as dinosaurs.

Long time readers might recall that I have mentioned actual Cadence tools or commands just a few times in the past four years of writing for them. To lift the veil a bit, they assure me that they have people who explain how to use the software. I’m here to help with board design more than ECAD tool operations. If you’re not already a Cadence user, then this story may be a bit wonky.

I’m here to talk about Design For Assembly (DFA) as it relates to the PCB footprint library. Specifically, the use of the DFA shape for spacing and the Place_Bound shape for representing the component itself. Long ago, the accepted approach to placement verification was to use the Place_Bound shape to include the personal space (courtyard) around a component. The component to component spacing in that case is a constant.

The amount of room allocated to a component is based entirely on how much oversize is included in the total of the two proximate components in terms of the Place_Bound shapes. When all of the components are at minimum spacing, there will be no gaps between the shapes. Conversely, if there is any room for components, it will be apparent by the fact that there is no shape covering an area when you turn on the layer of placement shapes. It’s this little fact right here that is preventing the ‘dinosaurs’ from agreeing to move forward.

The thing is that with this particular layer, the ECAD tool will export an .emn file that depicts the component at the size of the shape including the height attribute. The 3D image shows all or nearly all of the components touching its neighbors on all sides. I have a block of capacitors jammed together and it looks like a QFN package.

Reality, and step models are not like that. The air gaps are made out of air. Showing the space as space creates the granular detail that helps inform the mechanical engineer about our design intentions.

I’d go so far as to take it a step further with the passive devices that represent the component pads as rectangles with a height of 50 micrometers. Then, the full extent of the part will be manifested by a third shape that provides the length, width and height of the actual chip component. Now, if there is a mixture of step models and Place_Bound shapes, it will make a much truer representation of the 3-dimensional reality that we’re attempting to create.

Figure 3. Image Credit: Author - I prefer the three-shape approach for the typical two-pin components. It’s easier to imagine the final outcome.

Implementing this on the DFA layer would use a shape that covers the outer extents of the part or pad, whichever is sticking out the farthest. If the most extended feature is the pad, I would extend the DFA shape to include the soldermask expansion whether the padstack actually expands the mask or not.

The point of using this process is to make it easier for the library to evolve along with the technology. Changing the component spacing can be as easy as editing the values in the constraint manager.

The key to getting buy-in for this plan at Microsoft was to create a substitute layer that echoes the original Place_Bound layer but does not drive any design rule violations. Call it a “Courtyard” layer and include it with artwork that has the layers we would want turned on during placement. If the designer wants to use that layer for old-school placement, then they can.

The designer will most likely notice that the spacing will be corroborated and enforced by the DFA rules so long as they are enabled. Over time, it may become possible to overlap some of these courtyards as the placement spacing rules shrink generationally. The designer could still choose to place the parts in the old manner which would remain the low-tech, low-cost assembly standard.

Meanwhile, the minimum component spacing is not a static value for all time and can be tightened up or given extra space as required. I’ll leave you with one possible scenario where this can be deployed. Let’s say you’re going to do in-circuit test points and they can be pretty close to the short components, farther from the tall ones and farthest of all from each other.

Sample rules for test point distribution:

Test point to 0402 = 0.25 mm

Test point to connector = 0.5 mm

Test point to test point = 3 mm

The exact nature of how to categorize parts for placement is entirely up to you - or the librarian if you’re so lucky to have one in house. Different contract manufacturers have their guidelines. The amount of components versus the amount of board space will determine where the board fits on the density scale and thus who is the most suitable vendor for the job. Those values can be recalled from any board that is similar.

I’m not sure how long Cadence has had the DFA option but I’ve used it since 2013 and have made it mainstream in any company I’ve joined since then. It starts with one board. After the first board, the next one has a percentage already done. The third board and successive boards are likely to come down to a connector, maybe a crystal and a few ICs. Before long, all of the products and test fixtures are ready to be designed for assembly.

Going to Cadence Live showed me a way to sell this idea to the reluctant “designasaurs” out there; well worth the time. In any case, gaining an insight into Microsoft’s success will make it easier for me to introduce this component spacing tool wherever I go next. Perhaps, they’ll have evolved by then.