John Park's Webinar on Chiplets

Paul McLellan

Recently Cadence's John Park presented a webinar on Design Methodologies for Next-Generation Advanced Multi-Chip(let) Packaging.

Gordon Moore, famous for Moore's Law among other things, also predicted that this day would come. Over 50 years ago in his famous Electronics article where he extrapolated just four datapoints to a law that bears his name, he also said:

It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.

John pointed to three key trends that are driving the change now:

The desire for heterogeneous integration as an alternative to the SoC
Through-silicon-vias (TSVs) and fanout-wafer-level-packaging (FOWLP) driving more silicon content in packages
All major semiconductor foundries offering advanced single- and multi-chip packaging solutions, and often assembly design kits (ADKs)

For logic chips, cost per transistor has increased since about 2012 and the 28nm node. This was the last viable planar node. I say viable since there was a short-lived 20nm planar node, but leakage was so high that once FinFETs arrived it was quickly abandoned. Designing leading-edge SoCs has gotten prohibitively expensive. The largest chips (CPUs and GPUs for example) are reaching the reticle limits but, since large chips don't yield anyway, this is almost academic. There is also increasing amounts of RF and analog (5G anyone?) on chips, and analog has two problems with advanced nodes: it doesn't benefit from the advanced node, and the design needs to be recertified with test chips.

Disaggregated SoC

This has meant that system-in-package (SiP) has become a viable SoC alternative. This is what John calls "the disaggregated SoC". As he put it:

A chiplet is like a third version of IP that is physically realized and tested.

Designing one of these systems is more like designing a board than a chip, which leads to its own set of challenges since board design expertise is required for next-generation integration.

John feels that the final hurdles to chiplets going mainstream are falling. Todays' chiplet work is mostly specific to a single vendor, where the company doing the design of the chiplets is also the company doing the re-aggregation to an SiP. The next step will require commercialization of chiplets, meaning you can buy chiplets as opposed to always designing them yourself. Cadence actually released our first chiplet in 2019, called ULTRALINK. It provided SerDes I/O and die-to-die (D2D) interfaces to connect it. You can read about that in my post Die-to-Die Interconnect: The UltraLink D2D PHY IP.

There are two sets of challenges to commercialization of chiplets:

Standards for connectivity are needed, along with models for physical, thermal, and electromagnetic—basically, everything you need to connect up a chiplet if you can get your hands on one
Business models, so that you can get your hands on one—this needs to be settled before IP companies will do more than dip a toe in the water, like Cadence has with ULTRALINK

History

Chiplets in advanced packaging have been around for a long time. We used to call them multi-chip-modules or MCMs as far back as the 1970s. These were primarily used in expensive RF projects. Over time, different substrates have come along allowing 2.5D integration on silicon interposers, and full 3D integration where die are stacked on top of each other. FOWLP has meant that the price of using this technology has declined to the point that it can be used not just for expensive military projects but for products in the consumer market. Cadence has been involved with this technology since 1990, so for 30 years.

Design Tools and Flows

Okay, those are the market drivers as to why you might want to create a disaggregated SoCs. But how do you do it?

The first big decision is that Cadence offers you a choice of three different layout environments all of which work. These are Allegro, which comes from a PCB background. Virtuoso, which comes from a custom layout background. And Innovus, which comes from automated place and route digital design.

In the Q&A, John was asked how to choose and his guideline was that mostly it depends on the capacity that you will require in the tool. As he put it

If your design contains hundreds of thousands of instance you can use any of the three. If you have a million then Virtuoso or Innovus. For billions start with Innovus. Allegro technology is pretty unique and can put out formats for both board houses and foundries (GDS) depending on the manufacturing technology in use.

Over the top of it all is a tool that I sometimes call our "red-headed stepchild" since few people have ever heard of it. That is Integrity System Planner. It holds the master schematic that links up all the chiplets and can be used to drive the design flows, and also to do LVS to ensure that, when you are done, everything was hooked up correctly.

Virtuoso really comes into its own as a solution when you are mixing a lot of different technologies. It is a cross-platform solution that pulls together Virtuoso itself, Allegro, AWR AXIEM, EMX, CurvyCore (for silicon photonics), and Sigrity. It is the industry's first multi-chip(let) (multi-PDK) solution that provides system-level connectivity validation, automated layout parasitic feedback loop and true concurrent chip/package co-design.

Allegro X Advanced Package Designer is our design tool for packages. It also supports these more complex packages containing multi-die. Tens of thousands of designs have been taped-out with this technology. It supports all chiplet attach methods, such as bond-wire, flip-chip, stacked, embedded, and so on. It also supports all sorts of substrates such as glass, ceramic, silicon, laminate, and flex. It can perform multi-chiplet verification against assembly design rules (DFA, design for assembly). It also has DesignTrue, in-design design for manufacturability (DFM, not to be confused with the same term used for silicon where it typically means resolution enhancement technology). It can then create all the expected outputs required, such as BGA ball-maps, bond-wire diagrams, and so on.

Cadence has a whole family of tools for electromagnetic and thermal analysis: Sigrity, Clarity, Voltus, Celsius. These contain massively parallelized matrix solver and have virtually unlimited capacity (given enough machines in the cloud).

John then worked through an example. Since it was one of those really complicated Powerpoint builds, I'm not going to try and reproduce that here. If you are interested to see it, then you can watch the replay of the webinar. I'll put a link at the end of the post. The demo design included two chiplets in Virtuoso, and one imported from the outside world, so it was not a toy example.

Summary

Finally, John wrapped up. Here's his summary slide:

Watch the Webinar

You can watch a replay of the webinar.

If you have never read Gordon Moore's original Electronics magazine article, Intel has a copy Cramming More Components onto Integrated Circuits. I recommend reading it. I think, perhaps, the most amazing paragraph is the second one: