To Design For High Speed Data Rates

Printed circuit board design evolves over time and the rate of the evolution is not slowing down. High speed digital design becomes a key topic as we move forward.

By the time you read this, I’ll be officially old. Early retirement age is 62 and I was born in ‘62 so I’m eligible for those senior discounts. One of the things that happens as we advance in age is that time seems to go by even faster. We’ve seen so much that there is less novelty. We’re not plowing new furrows but rather deepening the ones we’ve tracked before.

I say that to say this. Circuits keep switching faster all the time. What worked in my early days no longer gets it done. My first computer didn’t have a hard drive. It had two floppy disk drives and they were the ones with 360 kilobytes rather than the smaller and stiffer 1.4 megs. I had DOS on one floppy and a modem driver on the other. The baud rate was only 1200 bytes

Now, look at the solid state thumb-drive on my keychain or the SD card inside my action camera. We’re talking up to two giga-bytes for SD cards. It doesn’t end there. SD has morphed to SDHC to reach the “high capacity” of 32 gigs. Then, we move up to SDXC where the extreme capacity goes to 2 terabytes. We’re not done. SDUC packs a whopping 128 terabytes. All of these form factors are also available as micro-SD cards to shrink things even further. Do you think we’re done? I doubt it.

Now, take 128 billion and divide it by 360 thousand. That's an improvement of over 350,000 times what I started with on my Zenith Z171 “luggable” machine from the late 1980’s. The potential storage is orders of magnitude beyond the ancient equipment while consuming a tiny fraction of the physical space of a floppy drive.

Reading that much data on the old gear would most likely still be in process all these decades later. That’s a long timeline but it illustrates what we face in today’s printed circuit board layouts. The exponential expansion of memory is met by processing pipelines that drive the intense applications found in mixed reality, robotics and other leading edge hardware.

Let’s Dig Into The High Speed Transmission Techniques

Low Voltage Differential Signaling (LVDS) is the cheat code to get more done with less power consumption. While very popular in mobile applications, the same efficiency is quite important in the data centers as well. From a board geometry standpoint, this is basically the same as the usual differential pair routing. Note that TTL requires 5V swings while CMOS runs on 3.3 volts.

Figure 1. Image Credit: Texas Instruments - LVDS incorporates smaller current swings which means that they make better neighbors in a crowded design.

The same benefits from typical differential pair routing include lowered EMI, rejection of external interference and higher data rates over single ended transmission lines. Meanwhile, the voltage requirements for LVDS are capped at 450 millivolts with a floor of 250 mV, an order of magnitude lower than TTL/CMOS voltage requirements.

The data rate skyrockets in this scenario. Part of the system may be on the older tech so it’s common to use serializers to combine numerous streams on the LVDS pair and deserializers to expand the LVDS signal back out to SATA, HDMI or other interfaces that use more wires for the same data rate. The same type of ser-des are used between fiber optic cables and copper traces on the network PC boards. Modern SOC’s make use of dozens of cores while the GPU’s have equivalent throughput but are marketed differently in order to boast even higher numbers. We have some work to do.

13 Tips For Good High Speed Layouts:

• Like any board, starting with good fundamental power integrity will solve many of the coexistence issues before they crop up.

• Placement supporting short line lengths while segregating components by power domain will help create an efficient routing result.

• Isolate noise sources such as crystals and other clocks with additional space and/or guard bands. That process helps keep the intersymbol coupling to a minimum.

• Short traces on top, longer ones on inner layers. We don’t want to use vias in general but they are the lesser of two issues when it comes to electromagnetic interference on longer runs.

• Use two ground vias that are placed in symmetry with the differential vias. If room is not available for ideal ground via placement, then put more than minimum spacing between the signal vias and the asymmetric ground via(s). Basically, don’t cozy up to one signal via if you can’t do the same with the other.

• Not just via symmetry, the gathers from the pins and vias ought to form a Y with equal spread.

• Do I even have to ask you not to cross over a gap in the reference plane?

• The gap between the via and the trace should be a bit more than the gap from the via to the supporting plane layer(s) to allow for misregistration.

• Avoid routing near the edges of the board if possible.

• Phase matching between the positive and negative elements of the pair should be addressed with an appropriate jog in the shorter trace so that the two lines are in sync before any length matching. If the two lines of a pair are a different length, you have less to work with for overall length matching.

• Dynamic phase matching is where that effort takes place on any bend. The idea is to keep the two waveforms in lock step for the entire flight. That’s where the inherent isolation really shines.

• Receive chains are typically more susceptible to EMI than transmit chains. Give them priority in terms of isolation.

• Use simulation in order to find and fix any unexpected issues. Everything done on the layout is a trade-off. Prototypes are still required but this cuts down on the number of cycles it takes to create a conforming design.

Figure 2. Image Credit: Author -  Known as probe cards, these are some challenging designs. They are typically circular to give us a chance of getting all of the signals from the chip to the perimeter with proper length matching.

Hardware is the scaffold that supports the software. The software, meanwhile, is rapidly expanding its reach into many aspects of our lives. Somewhere down the road, we may move into units of measure even smaller than a nano-meter to create new silicon. We have to keep up with those chips and manage all of that energy density with new solutions. Materials and processes evolve and our board designs are the link in between all of this progress.