Inter-Pair Skew

Key Takeaways

• Comparing the different types of skew in synchronous data lines.

• How to correct and prevent this skew in the design.

• Changes designers and manufacturers can make to bare board fabrication for skew minimization.

The serpentine patterns found in the bottom half of the image are indicative of inter-pair skew length tuning.

In electronic systems, timing is everything. Users expect rapid responses from complex systems with multiple avenues of interactivity. System functionality is defined at multiple levels by the transfer of data between different stages of the design. This seemingly seamless progression of data must follow strict timing protocols to prevent a loss of coherency or incorrect loading. 

The difference between the expected synchronous and actual arrival of time-constrained signals is known as the skew. Typically applied to the clock, it can also refer to the difference between signals in high-speed formats like DDR memory. This inter-pair skew (as it’s known) needs to be heeded according to the manufacturer’s instructions, lest the interface functionality be disrupted.

Inter-Pair Skew vs. Intra-Pair Skew

Correcting Inter-Pair Skew in Signal Interfaces

Ideally, synchronized signals need to arrive at their destination simultaneously to ensure there is no loss of data arising from timing issues. In reality, however, differences (even minute) in the propagation paths mean no two signals will ever arrive at the same time. For greater ease of use, components are forgiving and allow for some timing mismatch – known as clock skew – within tolerable limits. Timing mismatches are most heavily reliant on the length of the traces, resulting in two variations:

• Intra-pair skew between two lines of a differential pair, which indicates the timing difference between the positive and negative signal lines. Keeping the mismatch low between the two differential signals allows for more headroom and better noise protection in balanced lines. 
• Inter-pair skew indicates the timing difference between signals used in data formats that do not have an embedded clock signal. Inter-pair skew can cover both single-ended and differential pairs within a data format, making some signals doubly constrained by skew.

Correcting timing mismatches at the layout level is straightforward: designers will add additional length to signals until the intra- or inter-pair skew is within acceptable limits. Component placement is the first step to ensuring these signals are matched: align and move components from center lines such that the linear distance for signal paths are the same. Fixing length mismatches will differ depending on the type of skew: intra-pair skew will add length to the shorter of the two lines with bend compensation (ideally placed at or around the bend where the length diverges) while inter-pair skew will lengthen the signal with a serpentine pattern. Designers will want to avoid excessive gaps between differential pairs when compensating for bend as well as tight turn radii that result in extreme current density distribution and the ability for signals to bypass added length by arcing across gaps.

Compensating for inter-pair skew is generally more difficult than intra-pair skew even if the tolerance is higher (sometimes to the point of negligibility), because any length additions to one signal may push it above the maximum permittable skew relative to the other signals in its interface. To avoid a situation where adjusting the tuning results in a continuously moving skew target, start by finding the shortest routed length among the group of signals. This provides the floor and ideally makes it so that any additional length added is the minimum amount necessary to match the inter-pair skews. 

High-Speed Designs Require High-Speed Substrates

Controlling for inter-pair skew extends beyond the layout of the design. Adjusting for timing mismatches during layout is in some ways addressing the symptoms of skew rather than its causes. Board construction plays a significant factor: signals traveling over common board materials (e.g., 1080) do not encounter a constant dielectric due to the permittivity differences between the fiberglass and the epoxy. Mechanically, the combined fiberglass weave and epoxy resin matrix are critical to the fabrication of the board, but signals will experience different dielectric constants from the cumulative effect of the distance spent over fiberglass or epoxy. It’s difficult for designers to account for the difference in the fiberglass-epoxy matrix when routing, as there’s no way to tell where routed signals will end up relative to the matrix in the bare board. However, designers and fabricators have a few tricks at their disposal:

• The manufacturer can rotate the signaling image plane relative to the weave, reducing the incidence of the signal traces with the horizontal and vertical fiberglass weave.
• Only the signals susceptible to inter-pair skew are routed at non-45-degree angles. The designer can thus have more control over the total signal plane routing.
• Interface signals are routed in a zig-zag pattern that minimizes the planar distance traveled that is purely horizontal or vertical.

Fortunately, suppliers have concocted material solutions that help to minimize the effect of routing pathways. Substrate materials can include a tighter fiberglass weave that minimizes the area of fiberglass-locked epoxy between lines in the weave. As there is a smaller likelihood of variance in the substrate signals pass over, the average inter-pair skew over any distance drops.

When the Clock Is Ticking, Cadence ECAD Solutions Deliver

Inter-pair skew arises due to some inherent physical properties of printed circuit bare boards, but designers can collaborate with material suppliers to circumvent these issues while applying best layout practices of their own. Careful component placement and routing are key to minimizing the need for tuning while adjusting for inter-pair skew. Timing is vital for synchronous circuit functionality, but it is just one element of signal integrity designers will want to investigate for validation. Cadence’s robust  PCB Design and Analysis Software toolkit can quickly simulate and model complex circuitry for improved product development and DFM. Layout teams can rely on OrCAD PCB Designer to handle the modern demands of sprawling board features and shrinking time-to-market.

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