PMOS vs. NMOS

Key Takeaways

• The beginning of active switching elements and the transition to PMOS.

• The early manufacturing difficulties of NMOS and its growth to prominence.

• How CMOS leverages the advantages of PMOS and NMOS for a superior switching device.

CMOS technology (shown above in an image sensor) marked the end of the PMOS vs. NMOS dichotomy after decades of refinement

PMOS vs. NMOS FET technology: which is better? At one time, both offered manufacturing advantages over the other. They both still see individual usage. Yet it is their combined output that has vastly improved power performance in electronics over the past few decades.

The Switch from BJTs to FETs

To better understand the intricacies of PMOS vs. NMOS FETs, it is worth describing the underlying shared MOSFET theory. Until the 1970s, the primary active switching device in electronics was the bipolar junction transistor (BJT). In contrast to a FET, current flows in a BJT with both electrons and electron holes (the absence of an electron in a space that could be occupied by an electron). 

At the time of its invention, the BJT was a much simpler device to fabricate: it built on diode theory and could effectively be thought of as two back-to-back diodes sharing a p-silicon (positive or hole-rich) doped region for NPN BJTs or an n–silicon (negative or electron-rich) doped region for PNP BJTs. Unfortunately, this at-the-time ease of manufacturing has significant modern drawbacks relative to MOSFETs: difficulty in miniaturization, an inability to isolate minority and majority charge carriers, and greater power consumption.

Far and away, the majority of active switching elements in a circuit today are MOSFETs (specifically CMOS, but more on that in a bit) due to their superior performance across a wide range of applications. Unlike the alternating doped regions of the BJT, the MOSFET uses n- or p-wells (for NMOS and PMOS, respectively) on top of a substrate that is doped to be rich in the charge carrier opposite of the wells. Above the substrate, a polysilicate or metal gate sits atop an oxide layer that provides the control mechanism for a MOSFET: by driving the gate voltage to a particularly high or low threshold, the particular FET style can conduct between the source and drain terminals using its majority charge carrier. Compared to a p-n junction that is metallurgical (and thus a static material property during operation), the conduction of the MOSFET is field-induced, allowing for a greater level of control as well as reduced power demands.

MOSFETs Bring Producibility and Performance

The early dominance of the BJT would give way to the MOSFET, but it was PMOS technology that would first make headway in the 1970s. PMOS fabrication was far kinder to early MOSFET manufacturing sophistication, and even at this point it offered significant benefits over BJT production:

• Because MOSFETs are voltage-controlled instead of current-controlled, they required no quiescent current on the controlling terminal. This meant less power consumed and less heat dissipated.
• A MOSFET could occupy areas an order of magnitude smaller than that of BJTs.
• The manufacturing process was much simpler with single-step doping as opposed to four.

Despite some initial drawbacks, such as the need for a large negative voltage on the gate in early PMOS manufacturing and slow switching speeds owing to large gate capacitances, the industry would quickly refine production methods to improve efficiency in both areas. 

It’s worthwhile to take a brief digression to discuss one additional aspect of differentiating MOSFET operating modes:

• Enhanced mode MOSFETs are active when the gate voltage either exceeds the source voltage (NMOS) or subceeds the source voltage (PMOS). At zero gate voltage, these devices are off.
• Depletion mode MOSFETs are reversed - after a certain voltage threshold, PMOS gates turn off when the gate voltage is pulled above the source voltage and NMOS gates turn off when the gate voltage is pulled below the source voltage. If the threshold voltage has not been met, these devices remain active.

PMOS still suffered from some more severe operational issues, namely the need for multiple switching power supplies with high voltage requirements for enhanced mode as well as a large power draw (which was further compounded by a slow high-low transition state speed). Additionally, an inherent feature of the PMOS – the hole as the charge carrier – has a lower mobility than that of the electron. For these reasons and more, research and development would coalesce into NMOS fabrication. NMOS was immediately advantageous due to enhanced mode operation, eliminating the need for a negative voltage supply. Analogous and opposite to PMOS, however, NMOS suffered from slow low-high transition state speeds; unlike PMOS, depletion mode NMOS could run off a single power supply with improved low-high transition speeds and better interface with logic families like diode-transistor logic (DTL) and transistor-transistor logic (TTL).

Why PMOS vs. NMOS Isn’t a Choice at All

Is this the end of the story? Not quite – both NMOS and PMOS contain two critical flaws:

1. Transistors functioning as passive elements (i.e., pull-up and pull-down resistor networks) require constant power draw to remain active, which greatly increases power consumption.

2. Asymmetric logic inputs make the transistors more susceptible to noise pickup.

PMOS and NMOS have alternating strengths and weaknesses, and their combination – known as complementary metal-oxide-semiconductor (CMOS) – is the cornerstone of modern digital electronics. Joining the MOSFETs in this fashion means one is always conducting and one is always off; because formerly active elements can function during periods where FETs are switched off, the CMOS only incurs power losses during switching. Furthermore, this switching time is greatly reduced and the issues of longer low-high or high-low transition times are covered by the opposite FET in each pairing. 

Complement Your PDN Design With Cadence Solutions

The clear winner of the PMOS vs. NMOS logic families debate is a resounding “both” in the form of CMOS technology, which melds the strengths of each while conveniently compensating for the individual disadvantages. CMOS are ubiquitous in electronics for their superior size, power, and thermal characteristics, but there are still cases (such as high-speed circuits) where alternate active elements are better suited for performance. Development teams can benefit from Cadence’s suite of PCB Design and Analysis Software tools to simulate and model PDNs for optimal designs. Alongside the powerful and easy-to-use OrCAD PCB Designer, even complex boards can be laid out with DFM principles in record time.

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