How to Eliminate Clock Jitter

Key Takeaways

• Clock jitter represents the time domain instability of a clock signal. 

• Low clock jitter is ideal for the signal integrity of clock signals. 

• Terminating the trace properly is an appropriate method to eliminate the clock jitter caused by reflections.

Careful circuit layout can eliminate clock jitter in system clock circuits

In both digital and analog circuits, clock signals are used to run the system synchronously at high speed. Clocks are designed to be highly accurate and stable over time. However, the signal integrity of a clock signal can be compromised due to jitter and distortion. Clock jitter introduces uncertainty in the clock signal as well as circuit operations. As the signal propagates, the clock jitter increases. The effect of clock jitter is cumulative and degrades the communication channels, deteriorates the performance of the analog-to-digital converter, and reduces the signal-to-noise ratio. Learning how to eliminate clock jitter is a key skill for designers to grasp when designing clock trees for digital and analog systems. In this article, we will look at what clock jitter is as well as how to eliminate it.  

What Is Clock Jitter?

In digital communications, it is common for the signal window corresponding to the bit or symbol value to deviate from its ideal timing. The clock signals used to establish synchronization in a system are also vulnerable to timing variations. The edges of a clock signal often fail to be in phase with the ideal signal. Any timing deviations of the clock signal that edge from their ideal values are called clock jitter. Clock jitter represents the time domain instability of the clock signal.

The timing performance of clock signals is indicated using jitter. Clock jitter can be measured as the timing variation between the edges of the actual clock signal and the ideal waveform. The clock jitter is usually expressed in picoseconds. Low clock jitter is ideal for the signal integrity of clock signals. High clock jitter values project the poor timing performance of the system. The identification of the clock jitter type, its measurement, and the appropriate elimination method is critical for the performance of systems running synchronously at high speed. 

Types of Clock Jitter

Clock jitter can be classified into:

1. Random jitter - Random jitter is the main contributor to the overall jitter in a system. Random jitter is unbounded and can be described as intrinsic due to its presence in every system. It is difficult to diagnose and eliminate random jitter. 

2. Deterministic jitter - The deterministic jitter experienced in clock signals is due to certain specific reasons. Mostly, deterministic jitter is periodic and narrowband. Its repetitive nature makes it easy to detect and eliminate. Deterministic jitter can be sub-classified into:

1. Periodic jitter - Any jitter that is associated with a periodic frequency can be regarded as a periodic jitter. Typically, periodic jitter shares the same periodic frequency as the noise source. The jitter from the switching power supply is an example of periodic jitter.

2. Data-dependent jitter - Jitter that dynamically changes its duty cycles and gives irregular clock edges is called data-dependent jitter. Intersymbol interference is an example of data-dependent jitter. 

Jitter can be correlated or uncorrelated to the noise source. Regardless of the correlation to the noise source, clock jitter significantly influences system performance. Some contributing factors that aggravate the clock jitter effect on system performance include: 

• Noise sources
• Disturbances
• Thermal noise
• Loading conditions
• Power supply variations
• Interferences from adjacent circuits 

Common Effects of Clock Jitter

Unwanted effects caused by clock jitter are detrimental to high-speed system design. In digital communication systems, clock jitter causes errors, degrades channel performance, and introduces channel-to-channel interferences. The accuracy of the signal is deteriorated by clock jitter and increases the bit error rate in high-speed digital systems. In sampled systems such as analog-to-digital converters, the presence of clock jitter leads to the blurring of the reproduced signal by adding noise to the signals. The clock jitter corrupts the timing of the ADC and degrades the converter’s performance.

Let's take a look at how to eliminate clock jitter in various systems.

How to Eliminate Clock Jitter  

The key to learning how to eliminate clock jitter is to learn what causes it in the first place. The  two main reasons for clock jitter are:

1. Trace attenuation - The lossy trace material in a printed circuit board behaves like a low pass filter and attenuates the clock signal. As the trace length and frequency increase, the severity of the attenuation gets worse with the presence of high-frequency harmonics in the clock signal edges and thereby increases the jitter.
   Method of elimination - Choose a high swing mode to counter the trace attenuation and clock jitter. 

2. Reflection - The clock signal overshoots or undershoots due to reflections in the trace. The reflections are primarily caused by unterminated traces and impedance mismatches that intensify the clock jitter effect.
   Method of elimination - Terminate the trace properly. Series termination can be employed at the driving ends and parallel, and Thevenin or AC termination is best for the receiving end.  

Some other techniques to eliminate clock jitter include:

• Increase the slew rate of the clock signal. Improve the clock source by using a customized high-performance, low-jitter clock oscillator. 
• Provide pre-emphasis at the driver end to improve the high-frequency content in the clock signal and minimize deterministic clock jitter.
• Introduce equalization at the receiver end to prevent deterministic clock jitter.
• Use the reclocking solution through the phase-locking technique to minimize random clock jitter. 
• Use jitter attenuation circuits. 

Learning how to eliminate clock jitter is critical when designing system clock circuits. A careful circuit layout, proper filtering, the careful selection of clock hardware, and frequency division are some potential methods to eliminate clock jitter in system clock circuits. You can utilize Cadence software to design clock jitter-free digital and analog systems. Cadence offers a complete set of system analysis tools for designing clock-driven systems with minimum clock jitter.

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