Copper Thieving Improves Etch-and-Plate Results
Key Takeaways
CAM operators add copper plating (copper thieving) to average electroplating current across a board.
Does copper plating affect board bow and twist? There may be some benefits, but this is secondary to the plating/etching manufacturing concerns.
What should designers look for before approving an ECO from the CAM operator for copper thieving?
Copper patterning ensures copper features across the board plate and etch at similar rates.
Etching and plating are fundamental fabrication processes during PCB manufacturing. Most of today’s boards struggle with fitting all components and copper features within the board dimensions, so many wouldn’t expect any deviation in etching results besides obvious errors like failing to replace consumed etchant with more solution. Boards that are sparsely populated or those that feature extreme swings in local copper density may experience uneven plating or etching that affects reliability and performance. Copper thieving is a pattern added to better spread the copper placement on the board and average the results from the formerly high- and low-copper-density areas.
Copper Thieving Attributes and Considerations
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How Does Local Copper Density Affect Manufacturing?
Copper thieving is a fabrication process where manufacturers add small, repeatable copper patterns on the outer layers to promote downstream PCB manufacturing. Thieving has far more to do with manufacturing outcomes than anything design related. Since form follows function, it’s worthwhile for layout and engineers to understand the fabricator’s motivations for thieving.
The central purpose of copper thieving is to better “spread” the plating current around the board. During an electroplating process where the board immerses in a copper solution bath, areas of high copper density will sink more plating current than the low copper density areas—this distribution inequality leaves copper-dense areas with less plating and copper-sparse areas with more plating. Thieving, then, redistributes the copper density to more closely align local copper density with the average copper density of the board, ensuring that plating occurs uniformly and predictably.
Without redistribution, the plating process can suffer many adverse effects. Vias are especially liable for failure: boards with unequal copper distributions can produce barrel plating that fails acceptability criteria. Non-uniform or inadequate barrel plating – if undetected – can fail catastrophically during exposure to high-temperature processes like solder reflow, necessitating expensive rework. A combination of low-local copper feature density or thin traces can also greatly suffer without more consistent copper distribution; these traces are likely to experience undercutting, where more material etches away at the center of the trace as the top copper layer dissolves. The over-etched copper appears like an anvil cross-section – wide at the top, narrower towards the center, and then back to wide at the base – and loses significant structural integrity and electrical characteristics.
Some discussion on copper thieving focuses on its effect of balancing the copper distribution of the board during lamination to prevent bow and twist, which represent a deviation in the flatness and coplanarity of the board’s corners, respectively. Bow and twist are manufacturing issues that hinder all processes dependent on the planarity of the board; they are uncorrectable after production and result in board scrap. A common misconception of copper thieving is that it functions primarily as a copper balancing technique, but this is often a particular secondary effect. However, it’s inaccurate to state that the mechanical support offered by copper balancing is completely incorrect: boards with larger dimensions or substrates with less rigidity than standard fare like FR-4s may fortify structural integrity with this method.
Who’s Responsible for Copper Thieving?
The redistribution of copper is a necessary manufacturing process that adds elements to the board files. Accordingly, the fabricator should push the update back to the layout designer for final approval (or at least loop them in on the process). When discussing this adjustment with their manufacturers, designers will want to consider a few things:
Clearance - For a first design pass, most CAM operators will follow minimum clearance rules to place additional copper. However, this may not account for the layers adjacent to the top and bottom. Placing more copper above or below plane layers is acceptable, but signal layers pose an issue; thieving copper should not lay above or below these lines due to the potential effect on the electrical characteristics of the buried traces. Additionally, designers should verify planar clearance for features or circuits with clearance requirements that are more exacting than the general rule.
Net - Some fabricators may leave thieving copper floating rather than tied to a particular net (usually ground, but a power net can also be an option). If the copper does not assign to a net, it can couple with nearby traces and function as an antenna, severely impacting the signal integrity of the board. The threat of alterations to electrical performance down to the design intent of the board is another reason why the layout designer should be the one to finalize all changes to the copper features of the board.
Impedance - The size and proximity to traces can significantly affect the characteristic impedance of any lines; in essence, the designer is changing the transmission mode from a microstrip to a grounded coplanar waveguide. A design that has already incorporated these changes before sending off to the manufacturer will require fewer changes at an advanced design stage.
Cadence Is the Premier ECAD Solution for DFM
Copper thieving is a post-design process offered by fabricators that can enhance etching outcomes. The designer’s role in copper thieving is to provide the fab house with as much information about the board as possible, so fabrication can quickly implement design changes and pass along engineering change orders (ECOs) to the design team’s benefit. Primarily, the layout must ensure any added copper assigns to the correct net to eliminate floating copper and resultant signal integrity issues. Cadence’s PCB Design and Analysis Software suite has a comprehensive design rule check as part of its Constraint Manager for full DFM assurance. Alongside the fast and user-friendly OrCAD PCB Designer, the layout can confidently accelerate product development.
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